Resultados de Pesquisa

INGLÊS

Timing Performance Of Nanometer Digital Circuits Under Process Variations

de Jose Garcia Gervacio e Victor Champac

148,70€ + 10% EM CARTÃO

portes grátis

 This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications.
INGLÊS

Timing Performance Of Nanometer Digital Circuits Under Process Variations

de Jose Garcia Gervacio e Victor Champac

145,09€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications.
INGLÊS

The Blackout In Britain And Germany, 1939â€“1945

de Marc Wiggam

67,58€ + 10% EM CARTÃO

portes grátis

 This book is the first major study of the blackout in the Second World War. Arguing that the blackout formed an integral part in mobilising and legitimating British and German wartime discourses of community, fairness and morality, the book explores its profound impact on both countries.
INGLÊS

Models In Hardware Testing - Lecture Notes Of The Forum In Honor Of Christian Landrault

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Model based testing is the most powerful technique for testing hardware and software systems. This book describes the use of models at all the levels of hardware testing. It includes a description of fault models for nanoscaled CMOS technology.
INGLÊS

Soc (System-On-A-Chip) Testing For Plug And Play Test Automation

de Krishnendu Chakrabarty

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 System-on-a-Chip (SOC) integrated circuits composed of embedded cores are commonplace. Nevertheless, there remain several roadblocks to efficient system integration. This work contains thirteen contributions that address various aspects of SOC testing. It is suitable for researchers and students interested in various aspects of SOC testing.
INGLÊS

Defect Oriented Testing For Cmos Analog And Digital Circuits

de Manoj Sachdev

95,40€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.'' ... from the Foreword by Vishwani D. Agrawal
INGLÊS

Analog And Mixed-Signal Boundary-Scan - A Guide To The Ieee 1149.4 Test Standard

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 The Mixed-Signal Boundary-Scan Test Bus is the natural complement to the widely used Boundary-Scan IEEE Standard 1149.1, commonly known as JTAG. This title presents a comprehensive treatment of the design, application and structure of the IEEE 1149.4. It is suitable for researchers and professionals who need to understand IEEE Standard 1149.4.
INGLÊS

Reasoning In Boolean Networks - Logic Synthesis And Verification Using Testing Techniques

de Dominik Stoffel e Wolfgang Kunz

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Covers research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. This book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques.
INGLÊS

Introduction To Iddq Testing

de Paul J. Thadikaran e S. Chakravarty

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers.
INGLÊS

Formal Equivalence Checking And Design Debugging

de Kwang-Ting (Tim) Cheng e Shi-Yu Huang

211,34€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley
INGLÊS

Delay Fault Testing For Vlsi Circuits

de Angela Krstic e Kwang-Ting (Tim) Cheng

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech- niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
INGLÊS

Research Perspectives And Case Studies In System Test And Diagnosis

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 "System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is ¿any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail . System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress. The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the same problems and occasional disagreement between authors as to definitions or the importance of factors. ... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge ofthat science...". From the Preface
INGLÊS

Testability Concepts For Digital Ics - The Macro Test Approach

de A.P. Thijssen, F.P.M. Beenker e R.G. Bennetts

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Preface Testing Integrated Circuits for manufacturing defects includes four basic disciplines. First of all an understanding of the origin and behaviour of defects. Secondly, knowledge of IC design and IC design styles. Thirdly, knowledge of how to create a test program for an IC which is targeted on detecting these defects, and finally, understanding of the hardware, Automatic Test Equipment, to run the test on. All four items have to be treated, managed, and to a great extent integrated before the term 'IC quality' gets a certain meaning and a test a certain measurable value. The contents of this book reflects our activities on testability concepts for complex digital ICs as performed at Philips Research Laboratories in Eindhoven, The Netherlands. Based on the statements above, we have worked along a long- term plan, which was based on four pillars. 1. The definition of a test methodology suitable for 'future' IC design styles, 2. capable of handling improved defect models, 3. supported by software tools, and 4. providing an easy link to Automatic Test Equipment. The reasoning we have followed was continuously focused on IC qUality. Quality expressed in terms of the ability of delivering a customer a device with no residual manufacturing defects. Bad devices should not escape a test. The basis of IC quality is a thorough understanding of defects and defect models.
INGLÊS

Test Resource Partitioning For System-On-A-Chip

de Anshuman Chandra e Vikram Iyengar

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
INGLÊS

Elements Of Stil - Principles And Applications Of Ieee Std. 1450

de Gregory A. Maston, Julie N. Villar e Tony R. Taylor

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Principles and Applications of IEEE Std 1450.
INGLÊS

Verification By Error Modeling - Using Testing Techniques In Hardware Verification

de Katarzyna Radecka e Zeljko Zilic

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. This book brings the results in the direction of merging manufacturing test vector generation and verification. It discusses error fault models suitable for approaching the verification.
INGLÊS

High Performance Memory Testing - Design Principles, Fault Modeling And Self-Test

de R. Dean Adams

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Memory applications and the number of designs and the sheer number of bits on each design are critical. Based on the author's experience in memory design, memory reliability development and memory self test, this book is written for professionals and researchers, helping them understand the memories that are tested.
INGLÊS

Design For At-Speed Test, Diagnosis And Measurement

171,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Offers practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels. This book contains a complete design flow and analysis of the impact of embedded test on a design.
INGLÊS

Designer'S Guide To Built-In Self-Test

de Charles E. Stroud

237,84€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Written from a designer's perspective, this title describes the BIST approaches that have been proposed and implemented since 1980, along with their advantages and limitations. It pays particular attention to system-level use of BIST in order to maximize benefits of BIST through reduced testing time and cost as well as high diagnostic resolution.
INGLÊS

Testing Static Random Access Memories - Defects, Fault Models And Test Patterns

de Said Hamdioui

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Covers testing of one of the important semiconductor memories types. This book addresses testing of static random access memories (SRAMs), both single-port and multi-port. It introduces description of realistic fault models, based on defect injection and SPICE simulation.
INGLÊS

On-Line Testing For Vlsi

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Test functions (fault detection, diagnosis, error correction, repair, and more) that are applied concurrently while the system continues its intended function are defined as on-line testing. This book contains a selected set of articles that discuss many of the modern aspects of on-line testing.
INGLÊS

Multi-Chip Module Test Strategies

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 This volume of original research is designed for engineers interested in practical implementations of MCM test solutions and for designers looking for leading edge test and design-for-testability solutions for their next designs.
INGLÊS

From Contamination To Defects, Faults And Yield Loss - Simulation And Applications

de Jitendra B. Khare e Wojciech Maly

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.
INGLÊS

Efficient Branch And Bound Search With Application To Computer-Aided Design

de Michael L. Bushnell e Xinghao Chen

118,59€ + 10% EM CARTÃO

DISPONIBILIDADE IMEDIATA

 This text describes justification equivalence, in which duplication of computations is avoided in the dynamic branch-and-bound search process without using search decision trees. As well as covering the theoretical work, the book deals with applications, particularly ATPG for sequential circuits.
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