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Verification By Error Modeling eBook
Using Testing Techniques In Hardware Verification
idioma: inglês
Editor:
SPRINGER US, dezembro de 2005 ‧
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118,59€
10% DESCONTO
CARTÃO
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DISPONIBILIDADE IMEDIATA
Ebook para ADE
SINOPSE
Presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. This book brings the results in the direction of merging manufacturing test vector generation and verification. It discusses error fault models suitable for approaching the verification.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9780306487392 |
| Editor: | SPRINGER US |
| Data de Lançamento: | dezembro de 2005 |
| Idioma: | Inglês |
| Tipo de produto: | eBook |
| Formato e Compatibilidade: | PDF para ADE |
| Coleção: | Frontiers In Electronic Testing |
| Classificação Temática: |
eBooks em Inglês
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Engenharia
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Eletricidade e Energia
|
| EAN: | 9780306487392 |
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