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System-On-Chip Test Architectures eBook
Nanometer Design For Testability
idioma: inglês
Editor:
ELSEVIER SCIENCE, julho de 2010 ‧
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66,24€
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DISPONIBILIDADE IMEDIATA
Ebook para ADE
SINOPSE
A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9780080556802 |
| Editor: | ELSEVIER SCIENCE |
| Data de Lançamento: | julho de 2010 |
| Idioma: | Inglês |
| Tipo de produto: | eBook |
| Formato e Compatibilidade: | PDF para ADE |
| Coleção: | Systems On Silicon |
| Classificação Temática: |
eBooks em Inglês
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| EAN: | 9780080556802 |
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