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Verification Techniques For System-Level Design eBook
idioma: inglês
Editor:
ELSEVIER SCIENCE, julho de 2010 ‧
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78,16€
10% DESCONTO
CARTÃO
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DISPONIBILIDADE IMEDIATA
Ebook para ADE
SINOPSE
Explains how to verify SoC logic designs using 'formal' and 'semi-formal' verification techniques. This book covers various aspects of high-level formal and semi-formal verification techniques for system level designs.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9780080553139 |
| Editor: | ELSEVIER SCIENCE |
| Data de Lançamento: | julho de 2010 |
| Idioma: | Inglês |
| Tipo de produto: | eBook |
| Formato e Compatibilidade: | PDF para ADE |
| Coleção: | Systems On Silicon |
| Classificação Temática: |
eBooks em Inglês
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Arte
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Design e Ilustração
|
| EAN: | 9780080553139 |
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