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System-On-Chip Test Architectures eBook

Nanometer Design For Testability

by Laung-Terng Wang, Nur A. Touba e Charles E. Stroud
language: english
Publisher: ELSEVIER SCIENCE, July of 2010 ‧
66,24€
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A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.

System-On-Chip Test Architectures

Nanometer Design For Testability

by Laung-Terng Wang, Nur A. Touba e Charles E. Stroud

Property Description
ISBN: 9780080556802
Publisher: ELSEVIER SCIENCE
Release Date: July of 2010
Language: English
Format: eBook
File Format and Compatibility: PDF para ADE
Collection: Systems On Silicon
Categories: eBooks in English > Engineering > Electricity and Energy
EAN: 9780080556802