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Verification By Error Modeling
Using Testing Techniques In Hardware Verification
idioma: inglês
Editor:
SPRINGER-VERLAG NEW YORK INC., dezembro de 2010 ‧
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SINOPSE
Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9781441954022 |
| Editor: | SPRINGER-VERLAG NEW YORK INC. |
| Data de Lançamento: | dezembro de 2010 |
| Idioma: | Inglês |
| Dimensões: | 160 x 240 x 20 mm |
| Encadernação: | Capa mole |
| Páginas: | 216 |
| Tipo de produto: | Livro |
| Coleção: | Frontiers In Electronic Testing |
| Classificação Temática: |
Livros em Inglês
>
Engenharia
>
Eletricidade e Energia
|
| EAN: | 9781441954022 |
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