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Verification By Error Modeling eBook

Using Testing Techniques In Hardware Verification

by Katarzyna Radecka e Zeljko Zilic
language: english
Publisher: SPRINGER US, December of 2005 ‧
118,59€
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Ebook for ADE
Presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. This book brings the results in the direction of merging manufacturing test vector generation and verification. It discusses error fault models suitable for approaching the verification.

Verification By Error Modeling

Using Testing Techniques In Hardware Verification

by Katarzyna Radecka e Zeljko Zilic

Property Description
ISBN: 9780306487392
Publisher: SPRINGER US
Release Date: December of 2005
Language: English
Format: eBook
File Format and Compatibility: PDF para ADE
Collection: Frontiers In Electronic Testing
Categories: eBooks in English > Engineering > Electricity and Energy
EAN: 9780306487392

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