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Verification By Error Modeling

Using Testing Techniques In Hardware Verification

by Katarzyna Radecka e Zeljko Zilic
language: english
Publisher: SPRINGER-VERLAG NEW YORK INC., December of 2010 ‧
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Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Verification By Error Modeling

Using Testing Techniques In Hardware Verification

by Katarzyna Radecka e Zeljko Zilic

Property Description
ISBN: 9781441954022
Publisher: SPRINGER-VERLAG NEW YORK INC.
Release Date: December of 2010
Language: English
Dimensions: 160 x 240 x 20 mm
Cover: Softcover
Pages: 216
Format: Book
Collection: Frontiers In Electronic Testing
Categories: Books in English > Engineering > Electricity and Energy
EAN: 9781441954022

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