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Principles Of Verifiable Rtl Design eBook
A Functional Coding Style Supporting Verification Processes In Verilog
language: english
Publisher:
SPRINGER US, May of 2007 ‧
see product details
137,27€
20% OFF
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IMMEDIATE AVAILABILITY
Ebook for ADE
SYNOPSIS
Discusses topics such as: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL; and more 'bad stuff'. This work tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes.
DETAILS
| Property | Description |
|---|---|
| ISBN: | 9780306476310 |
| Publisher: | SPRINGER US |
| Release Date: | May of 2007 |
| Language: | English |
| Format: | eBook |
| File Format and Compatibility: | PDF para ADE |
| Categories: |
eBooks in English
>
Engineering
>
Electricity and Energy
|
| EAN: | 9780306476310 |