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Introduction To Logic Synthesis Using Verilog Hdl eBook
idioma: inglês
Editor:
Springer International Publishing, maio de 2022 ‧
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33,11€
10% DESCONTO
CARTÃO
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DISPONIBILIDADE IMEDIATA
Ebook para ADE
SINOPSE
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9783031797439 |
| Editor: | Springer International Publishing |
| Data de Lançamento: | maio de 2022 |
| Idioma: | Inglês |
| Tipo de produto: | eBook |
| Coleção: | Synthesis Lectures On Digital Circuits & Systems |
| Classificação Temática: |
eBooks em Inglês
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Engenharia
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Engenharia Geral
eBooks em Inglês > Engenharia > Eletricidade e Energia |
| EAN: | 9783031797439 |
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