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Logic Synthesis And Verification Algorithms
idioma: inglês
Editor:
SPRINGER-VERLAG NEW YORK INC., março de 2013 ‧
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SINOPSE
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9781475770360 |
| Editor: | SPRINGER-VERLAG NEW YORK INC. |
| Data de Lançamento: | março de 2013 |
| Idioma: | Inglês |
| Dimensões: | 700 x 1,000 x 121 mm |
| Encadernação: | Capa mole |
| Páginas: | 564 |
| Tipo de produto: | Livro |
| Classificação Temática: |
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| EAN: | 9781475770360 |