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Logic Synthesis And Verification Algorithms

by Gary D. Hachtel e Fabio Somenzi
language: english
Publisher: SPRINGER-VERLAG NEW YORK INC., March of 2013 ‧
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Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).

Logic Synthesis And Verification Algorithms

by Gary D. Hachtel e Fabio Somenzi

Property Description
ISBN: 9781475770360
Publisher: SPRINGER-VERLAG NEW YORK INC.
Release Date: March of 2013
Language: English
Dimensions: 700 x 1,000 x 121 mm
Cover: Softcover
Pages: 564
Format: Book
Categories: Books in English > Others
EAN: 9781475770360