10% OFF

Logic Synthesis And Soc Prototyping

Rtl Design Using Vhdl

by Vaibbhav Taraate
language: english
Publisher: SPRINGER VERLAG, SINGAPORE, January of 2021 ‧
101,38€
10% OFF CARD
free shipping
Sell ​​your book
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design.

Logic Synthesis And Soc Prototyping

Rtl Design Using Vhdl

by Vaibbhav Taraate

Property Description
ISBN: 9789811513169
Publisher: SPRINGER VERLAG, SINGAPORE
Release Date: January of 2021
Language: English
Dimensions: 155 x 235 x 20 mm
Cover: Softcover
Pages: 251
Format: Book
Categories: Books in English > Engineering > Electricity and Energy
Books in English > Others
EAN: 9789811513169