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Asic Design And Synthesis

Rtl Design Using Verilog

by Vaibbhav Taraate
language: english
Publisher: SPRINGER VERLAG, SINGAPORE, January of 2021 ‧
243,33€
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This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

Asic Design And Synthesis

Rtl Design Using Verilog

by Vaibbhav Taraate

Property Description
ISBN: 9789813346413
Publisher: SPRINGER VERLAG, SINGAPORE
Release Date: January of 2021
Language: English
Dimensions: 155 x 235 x 20 mm
Cover: Hardcover
Pages: 330
Format: Book
Categories: Books in English > Engineering > Electricity and Energy
EAN: 9789813346413