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Asic Design And Synthesis eBook

Rtl Design Using Verilog

by Vaibbhav Taraate
language: english
Publisher: Springer Nature Singapore, January of 2021 ‧
158,34€
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This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

Asic Design And Synthesis

Rtl Design Using Verilog

by Vaibbhav Taraate

Property Description
ISBN: 9789813346420
Publisher: Springer Nature Singapore
Release Date: January of 2021
Language: English
Format: eBook
File Format and Compatibility:
Categories: eBooks in English > Engineering > Electricity and Energy
eBooks in English > Computing > Hardware
EAN: 9789813346420
Acessibilidade: Ver características de acessibilidade indicadas pelo editor