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Principles Of Verifiable Rtl Design eBook
A Functional Coding Style Supporting Verification Processes In Verilog
idioma: inglês
Editor:
SPRINGER US, maio de 2007 ‧
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137,27€
20% DESCONTO
IMEDIATO
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DISPONIBILIDADE IMEDIATA
Ebook para ADE
SINOPSE
Discusses topics such as: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL; and more 'bad stuff'. This work tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes.
DETALHES
| Propriedade | Descrição |
|---|---|
| ISBN: | 9780306476310 |
| Editor: | SPRINGER US |
| Data de Lançamento: | maio de 2007 |
| Idioma: | Inglês |
| Tipo de produto: | eBook |
| Formato e Compatibilidade: | PDF para ADE |
| Classificação Temática: |
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| EAN: | 9780306476310 |