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Datacenter As A Computer - An Introduction To The Design Of Warehouse-Scale Machines, Second Edition

by Jimmy Clidaras e Luis Andre Barroso

105,99€ + 10% CARD

 <p>As computation continues to move into the cloud, the computing platform of interest no longer resembles a pizza box or a refrigerator, but a warehouse full of computers. These new large datacenters are quite different from traditional hosting facilities of earlier times and cannot be viewed simply as a collection of co-located servers. Large portions of the hardware and software resources in these facilities must work in concert to efficiently deliver good levels of Internet service performance, something that can only be achieved by a holistic approach to their design and deployment. In other words, we must treat the datacenter itself as one massive warehouse-scale computer (WSC). We describe the architecture of WSCs, the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. We hope it will be useful to architects and programmers of today’s WSCs, as well as those of future many-core platforms which may one day implement the equivalent of today’s WSCs on a single board.</p><p><b>Notes for the Second Edition</b></p><p>After nearly four years of substantial academic and industrial developments in warehouse-scale computing, we are delighted to present our first major update to this lecture. The increased popularity of public clouds has made WSC software techniques relevant to a larger pool of programmers since our first edition. Therefore, we expanded Chapter 2 to reflect our better understanding of WSC software systems and the toolbox of software techniques for WSC programming. In Chapter 3, we added to our coverage of the evolving landscape of wimpy vs. brawny server trade-offs, and we now present an overview of WSC interconnects and storage systems that was promised but lacking in the original edition. Thanks largely to the help of our new co-author, Google Distinguished Engineer Jimmy Clidaras, the material on facility mechanical and power distribution design has been updated and greatly extended(see Chapters 4 and 5). Chapters 6 and 7 have also been revamped significantly. We hope this revised edition continues to meet the needs of educators and professionals in this area.</p>
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Primer On Memory Consistency And Cache Coherence

by Daniel Sorin, David Wood e Mark Hill

119,24€ + 10% CARD

 Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies
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On-Chip Networks

by Li-Shiuan Peh e Natalie Enright

105,99€ + 10% CARD

 With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions
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Datacenter As A Computer - An Introduction To The Design Of Warehouse-Scale Machines

by Luiz Barroso e Urs Hoelzle

105,99€ + 10% CARD

 As computation continues to move into the cloud, the computing platform of interest no longer resembles a pizza box or a refrigerator, but a warehouse full of computers. These new large datacenters are quite different from traditional hosting facilities of earlier times and cannot be viewed simply as a collection of co-located servers. Large portions of the hardware and software resources in these facilities must work in concert to efficiently deliver good levels of Internet service performance, something that can only be achieved by a holistic approach to their design and deployment. In other words, we must treat the datacenter itself as one massive warehouse-scale computer (WSC). We describe the architecture of WSCs, the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. We hope it will be useful to architects and programmers of today''s WSCs, as well as those of future many-core platforms which may one day implement the equivalent of today''s WSCs on a single board. Table of Contents: Introduction / Workloads and Software Infrastructure / Hardware Building Blocks / Datacenter Basics / Energy and Power Efficiency / Modeling Costs / Dealing with Failures and Repairs / Closing Remarks
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Transactional Memory

by James R. Larus e Ravi Rajwar

43,71€ + 10% CARD

 The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, runtime system, and hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early summer 2006.
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Quantum Computing For Computer Architects

by Frederic T. Chong e Tzvetan S. Metodi

43,71€ + 10% CARD

 Quantum computation may seem to be a topic for science fiction, but small quantum computers have existed for several years and larger machines are on the drawing table. These efforts have been fueled by a tantalizing property: while conventional computers employ a binary representation that allows computational power to scale linearly with resources at best, quantum computations employ quantum phenomena that can interact to allow computational power that is exponential in the number of "quantum bits" in the system. Quantum devices rely on the ability to control and manipulate binary data stored in the phase information of quantum wave functions that describe the electronic states of individual atoms or the polarization states of photons. While existing quantum technologies are in their infancy, we shall see that it is not too early to consider scalability and reliability. In fact, such considerations are a critical link in the development chain of viable device technologies capable oforchestrating reliable control of tens of millions quantum bits in a large-scale system. The goal of this lecture is to provide architectural abstractions common to potential technologies and explore the systemslevel challenges in achieving scalable, fault-tolerant quantum computation. The central premise of the lecture is directed at quantum computation (QC) architectural issues. We stress the fact that the basic tenet of large-scale quantum computing is reliability through system balance: the need to protect and control the quantum information just long enough for the algorithm to complete execution. To architectQCsystems, onemust understand what it takes to design and model a balanced, fault-tolerant quantum architecture just as the concept of balance drives conventional architectural design. For example, the register file depth in classical computers is matched to the number of functional units, the memory bandwidth to the cache miss rate, or the interconnect bandwidth matched to the compute power of each element of a multiprocessor. We provide an engineering-oriented introduction to quantum computation and provide an architectural case study based upon experimental data and future projection for ion-trap technology.We apply the concept of balance to the design of a quantum computer, creating an architecture model that balances both quantum and classical resources in terms of exploitable parallelism in quantum applications. From this framework, we also discuss the many open issues remaining in designing systems to perform quantum computation.
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On Architecting Fully Homomorphic Encryption-Based Computing Systems

by Ajay Joshi e Rashmi Agrawal

~~81,10€~~ 56,77€ 30% OFF

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 This book provides an introduction to the key concepts of Fully Homomorphic Encryption (FHE)-based computing, and discusses the challenges associated with architecting FHE-based computing systems.
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Shared-Memory Synchronization

by Michael L. Scott e Trevor Brown

~~52,99€~~ 47,69€ 10% OFF

 <div>This book offers a comprehensive survey of shared-memory synchronization, with an emphasis on "systems-level" issues. It includes sufficient coverage of architectural details to understand correctness and performance on modern multicore machines, and sufficient coverage of higher-level issues to understand how synchronization is embedded in modern programming languages.</div><div><br></div><div>The primary intended audience for this book is "systems programmers"—the authors of operating systems, library packages, language run-time systems, concurrent data structures, and server and utility programs. Much of the discussion should also be of interest to application programmers who want to make good use of the synchronization mechanisms available to them, and to computer architects who want to understand the ramifications of their design decisions on systems-level code.</div>
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On Architecting Fully Homomorphic Encryption-Based Computing Systems

by Ajay Joshi e Rashmi Agrawal

59,61€ + 10% CARD

 This book provides an introduction to the key concepts of Fully Homomorphic Encryption (FHE)-based computing, and discusses the challenges associated with architecting FHE-based computing systems.
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Disaster Medicine Pocket Guide: 50 Essential Questions - Work Of The French Society Of Disaster Medicine

~~67,58€~~ 47,31€ 30% OFF

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 This book is intended for all healthcare and emergency staff, doctors, paramedics or first aiders in ambulances or in emergency services who might come to deal with a massive influx of injured, poisoned, or traumatised victims.
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A Primer On Memory Persistency

by Aasheesh Kolli, Thomas F. Wenisch e Vaibhav Gogte

~~66,23€~~ 46,36€ 30% OFF

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 This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs).
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Principles Of Secure Processor Architecture Design

by Jakub Szefer

72,86€ + 10% CARD

 <p>With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered).</p> <p>This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.</p>
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Helping Adults To Grow Up - A Practitioner'S Guide To Stage Climbing

by Michael S., Ph.D. Broder

~~87,86€~~ 61,50€ 30% OFF

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 This book presents Stage Climbing, an innovative seven stage developmental model as a new tool to help practitioners recognize cognitions, attitudes and behaviors-- typical of different life stages and thus levels of maturity-- in order to select the most effective treatment interventions with adult clients.
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In-/Near-Memory Computing

by Arun Subramaniyan, Daichi Fujiki, Reetuparna Das e Xiaowei Wang

~~74,34€~~ 52,04€ 30% OFF

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 While in- and near-memory computing can circumvent overheads related to data movement, it comes at the cost of restricted flexibility of data representation and computation, design challenges of compute capable memories, and difficulty in system and software integration.
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Robotic Computing On Fpgas

by Bo Yu, Shaoshan Liu, Yu Wang e Zishen Wan

~~74,34€~~ 52,04€ 30% OFF

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 This book provides a thorough overview of the state-of-the-art field-programmable gate array (FPGA)-based robotic computing accelerator designs and summarizes their adopted optimized techniques.
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Ai For Computer Architecture - Principles, Practice, And Prospects

by Daniel Jimenez, Drew Penney e Lizhong Chen

~~74,34€~~ 52,04€ 30% OFF

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 The book further analyzes current practice to highlight useful design strategies and identify areas for future work, based on optimized implementation strategies, opportune extensions to existing work, and ambitious long term possibilities.
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Deep Learning Systems - Algorithms, Compilers, And Processors For Large-Scale Production

by Andres Rodriguez

~~74,34€~~ 52,04€ 30% OFF

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 The book details advancements and adoption of DL models in industry, explains the training and deployment process, describes the essential hardware architectural features needed for today's and future models, and details advances in DL compilers to efficiently execute algorithms across various hardware targets.
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Data Orchestration In Deep Learning Accelerators

by Ananda Samajdar, Angshuman Parashar, Hyoukjun Kwon, Michael Pellauer e Tushar Krishna

~~74,34€~~ 52,04€ 30% OFF

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 This Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM.
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Efficient Processing Of Deep Neural Networks

by Joel S. Emer, Tien-Ju Yang, Vivienne Sze e Yu-Hsin Chen

~~81,10€~~ 56,77€ 30% OFF

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 This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics.
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A Primer On Memory Consistency And Cache Coherence, Second Edition

by Daniel J. Sorin, David A. Wood, Mark D. Hill e Vijay Nagarajan

~~74,34€~~ 52,04€ 30% OFF

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 Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system.
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Innovations In The Memory System

by Rajeev Balasubramonian

~~74,34€~~ 52,04€ 30% OFF

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 This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
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Cache Replacement Policies

by Akanksha Jain e Calvin Lin

~~37,84€~~ 26,49€ 30% OFF

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 This book summarizes the landscape of cache replacement policies for CPU data caches. Each of these categories is then divided into three subcategories that describe different approaches to solving the cache replacement problem, along with summaries of significant work in each category.
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The Datacenter As A Computer - Designing Warehouse-Scale Machines, Third Edition

by Luiz Andre Barroso, Parthasarathy Ranganathan e Urs Holzle

~~60,82€~~ 42,57€ 30% OFF

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 This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day.
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Deep Learning For Computer Architects

by Brandon Reagen, David Brooks, Gu-Yeon Wei, Paul Whatmough e Robert Adolf

~~67,58€~~ 47,31€ 30% OFF

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 Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science.
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