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Verification Techniques For System-Level Design
language: english
Publisher:
ELSEVIER SCIENCE & TECHNOLOGY, December of 2007 ‧
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SYNOPSIS
Explains how to verify SoC logic designs using 'formal' and 'semi-formal' verification techniques. This book covers various aspects of high-level formal and semi-formal verification techniques for system level designs.
DETAILS
| Property | Description |
|---|---|
| ISBN: | 9780123706164 |
| Publisher: | ELSEVIER SCIENCE & TECHNOLOGY |
| Release Date: | December of 2007 |
| Language: | English |
| Cover: | Hardcover |
| Pages: | 256 |
| Format: | Book |
| Categories: |
Books in English
>
Engineering
>
Electricity and Energy
|
| EAN: | 9780123706164 |