Capa do artigo Improving Performance And Reducing Power With Hardware Acceleration - Static Timing Analysis Based Transformations Of Combinational Logic In A High Level Asic Synthesis Flow

Improving Performance And Reducing Power With Hardware Acceleration - Static Timing Analysis Based Transformations Of Combinational Logic In A High Level Asic Synthesis Flow

by Alex K. Jones e Colin J. Ihrig
language: english
Publisher: VDM Verlag, December of 2008 ‧
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Improving Performance And Reducing Power With Hardware Acceleration - Static Timing Analysis Based Transformations Of Combinational Logic In A High Level Asic Synthesis Flow

by Alex K. Jones e Colin J. Ihrig

Property Description
ISBN: 9783639106909
Publisher: VDM Verlag
Release Date: December of 2008
Language: English
Cover: Softcover
Pages: 96
Format: Book
Categories: Books in English > Computing > Other Applications
Books in English > Computing > Introduction to Computing
EAN: 9783639106909

ALEX K. JONES

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COLIN J. IHRIG

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